(Portions of the technical material contained in this section may not be prior art.)
State of the art radio-frequency (RF) electrical circuits use large quantities of inductors. Many of these circuits are used in hand held wireless products. Accordingly, miniaturization of passive devices and passive device circuits is an important goal in RF device technology.
Recent advances in passive device technology have produced integrated passive devices (IPDs) wherein inductors, capacitors, and resistors are integrated on a single compact substrate. IPD substrates are large, and preferably made of silicon, but in some cases ceramic. More details on IPD structures and their manufacture can be found in U.S. application Ser. No. 11/030,754, filed Jan. 6, 2005, which is incorporated herein by reference.
Design of inductor components in these IPDs usually has two goals, high Q and a compact space. In general, inductor devices require conductors that run side-by-side along a substantial length. The RF current flows in the same direction through the side-by-side conductors so that the magnetic flux lines are in the same phase. This results in a large mutual inductance. Straight conductors, that is, elongated pairs of runners, achieve this goal in principle but consume excessive linear space in a conventional IPD. Spiral shaped runners, and nested squares or rectangles of runners, achieve the desired result in a more compact space.
The other goal, high Q, seeks high performance (inductance value) with low power loss. Several factors influence the Q factor. The inductance value depends (inter alia) on the length and spacing of the runners. The power loss depends to first order on the conductivity of the metal. The conductivity is dependent on the width and thickness of the runners. Thus several parameters enter the design considerations for high Q inductors.
In state of the art integrated passive devices some of the design goals are in conflict. For example, for small, compact, IPDs it is desirable to shrink the interconnections. This increases the resistance of the inductor runners and reduces the Q of the inductor. To offset this, the conductivity of the runner may be increased by switching from aluminum, the standard metal, to copper. Another proposal is to coat the aluminum runners with a copper strike layer.
Yet another approach is to increase the length of the inductor. Nominally it would appear that increases in inductor length require increased surface area. However, it has been recognized that inductor design is not restricted to two dimensions. Accordingly, three-dimensional IPD devices, i.e. devices built on multiple levels, have been developed. Multiple level inductors produce multiplied inductor values for a given surface area. For example, see Yin et al., Double-Level Spiral Inductors With Multiple Via Interconnects on GaAs Substrates, IEEE TRANSACTIONS ON MAGNETICS, VOL. 40, NO. 3, MAY 2004. This paper describes various structural parameters of stacked, multilevel inductors, and is incorporated herein by reference.
With the proven value of two-level inductors, additional levels, for example, four levels, would appear to be the next step. However, each added multiple level in an IPD substrate increases cost. This is especially the case where the multiple levels serve only the inductor elements.
More efficient designs for three-dimensional IPDs would allow continued progress in IPD technology.